1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a level shifter.
2. Description of the Related Art
A semiconductor integrated circuit may include a level shifter. The level shifter may be used for signal transmission between internal blocks using heterogeneous driving voltages. The level shifter may also adjust swing levels from an input signal to an output signal.
The level shifter may lower or raise the swing level of the input signal.
FIG. 1 is a diagram illustrating a conventional level shifter.
Referring to FIG. 1, the level shifter includes first and second PMOS transistors P1 and P2, first and second NMOS transistors N1 and N2, and an inverter 110.
The first NMOS transistor N1 receives an input signal IN, which swings between a first power voltage VDD1 (not illustrated) and a ground voltage VSS, through its gate. The second NMOS transistor N2 receives an inverted input signal INB, which is an inverted signal of the input signal IN that is inverted through the inverter 110, through its gate. The first and second NMOS transistors N1 and N2 are grounded at their sources.
The first PMOS transistor P1 is coupled to a drain of the first NMOS transistor N1 at its drain and coupled to a drain of the second NMOS transistor N2 at its gate. The second PMOS transistor P2 is coupled to the drain of the second NMOS transistor N2 at its drain and coupled to the drain of the first NMOS node N1 at its gate. The first and second PMOS transistors P1 and P2 are grounded at their sources.
The level shifter changes a swing range of the input signal IN from between the first power voltage VDD1 and the ground voltage VSS to between a second power voltage VDD2 and the ground voltage VSS. The second power voltage VDD2 has a voltage level higher than the first power voltage VDD1.
Operation of the level shifter with such cross-coupled latch scheme is as follows.
When the level of the input signal IN is changed from the ground voltage VSS to the first power voltage VDD1, the first NMOS transistor N1 is turned on and discharges a node MID, where the first PMOS transistor P1 is coupled to the drain of the second NMOS transistor N2 with its gate, to the ground voltage VSS. The second PMOS transistor P2 is coupled to the drain of the second NMOS transistor N2 with its drain. Due to the node MID being discharged to the ground voltage VSS, the second PMOS transistor P2 is turned on to drive an output node OUT to the second power voltage VDD2.
When the level of the input signal IN is changed from the ground voltage VSS to the first power voltage VDD1, the first NMOS transistor N1 receiving the input signal IN is turned on and the second NMOS transistor N2 receiving the inverted input signal INB is turned off, and thus the node MID is discharged to the ground voltage VSS.
At that time, the second PMOS transistor P2 is slightly turned on due to the voltage of the node MID and may not promptly raise the voltage of the output node OUT from the ground voltage VSS to the second power voltage VDD2, which turns on the first PMOS transistor P1. Thus, a through-current flowing from the second power voltage VDD2 to the ground voltage VSS is generated through the first NMOS transistor N1 turned on by the input signal IN and the turned-on first PMOS transistor P1, and thus generates a current-fighting. The current-fighting indicates a current crash between the through-current having the level of the second power voltage VDD2 through the first. PMOS transistor P1 and a current having the level of the first power voltage VDD1 through the first NMOS transistor N1.
As a result, the voltage of the node MID is lowered because of the current driving difference between the two transistors. Thus, the second PMOS transistor P2 is turned on and the voltage level of the output node OUT is raised to the second power voltage VDD2. Furthermore, the first PMOS transistor P1 is turned off and the node MID is grounded.
When the voltage difference between the first and second power voltages VDD1 and VDD2 are great and the current sinking capability of the first and second NMOS transistors N1 and N2 is not enough, the voltage level of the node MID may not turn on the first PMOS transistor P1, and thus the level shifter may not transmit the expected signal. Further, the difference in the pull-up/pull-down capability may occur and duty error may increase due to process skew and the voltage difference between the first and second power voltages VDD1 and VDD2.